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I'm trying to understand serializer/deserializer hardware, so am taking it slow.
I think I've constructed a simple serial_to_parallel data converter to take in a serial stream of data and after 4 clocks on the input stream side, I'd have a single 4-bit word of data that I could theoretically consume in one clock cycle. Code is below:
Now I'm trying to think of how this 'serial_data_in' would come into FPGA and how I'd clock in the 'parallel_data_out' as fast as possible, internal to the FPGA. I assume the 'clk_in' is coming with the data_stream, and I've used a PLL or something to phase align this 'clk_in' internally to the FPGA with what is external to FPGA at the pins. So clocking the shift_reg with this clock should be fine. Also I'm shifting in LSB first and assuming no backpressure/throttling is possible (not sure if this is realistic). My questions are:
so after 4 clock pulses of 'clk_in' with the right 'shift_en', I have a complete 4 bit word ready for processing. What's the fastest way to take in this 4 bit word to do stuff into another clock domain? One thought I had is maybe it's just an async fifo where I write in this 4 bit parallel word into the write side using a phase aligned clock that is 1/4 the frequency of clk_in, and read out with whatever read_clock I want (assume fifo is sized appropriately).
should I use an async fifo first to convert the serial stream to the read_clock domain and stream a serial_data stream out synchronized to the read_clock domain I want before creating a 4 bit parallel word?
do I need a counter that counts 4 successive cycles of 'clk_in' and puts out a flag so that I know a complete 4-bit word is ready?
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is there any case where I'd need a valid bit along with the serial_data_in input stream? Wouldn't the shift_en signal that indicates the desire to shift in be enough?